PXB4330 Datasheet, PDF (155/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 48 IMRU
Interrupt Mask Register Upstream
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
IMRU
D2_H
Written by CPU to control interrupt signal effective
events
Bit
15
14
13
12
11
10
9
8
IMRU(15:8)
Bit
7
6
5
4
3
2
1
0
IMRU(7:0)
IMRU(15:0)
Interrupt Mask Upstream
Each bit controls whether the corresponding interrupt indication in
register ISRU (same bit location) activates the interrupt signal:
1
Interrupt indication masked.
The interrupt signal is not activated upon this event.
0
Interrupt indication unmasked.
The interrupt signal is activated upon this event.
Data Sheet
6-155
09.99