PXB4330 Datasheet, PDF (114/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 23 LEVL0
Upstream Scheduler Lower Threshold Reached Indication Register 0
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read
0000_H
45_H
Read by CPU
Bit
15
14
13
12
11
10
9
8
SchedIndLow(15:8)
Bit
7
6
5
4
3
2
1
0
SchedIndLow(7:0)
SchedIndLow
(15:0)
These bits represent the respective upstream scheduler(15:0) and
indicate that its lower scheduler threshold configured in the SOT0
table is reached or exceeded; that is, at least as many cells are
currently stored as specified by the LDSTL threshold value:
bit i=1 Scheduler i lower threshold reached or exceeded.
Data Sheet
6-114
09.99