PXB4330 Datasheet, PDF (136/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Register 38 SADRU/SADRD
Upstream/Downstream SCTI Address Registers
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
SADRU
90_H
SADRD
B0_H
Written and Read by CPU to maintain the SCTI tables
Bit
15
14
13
12
11
10
9
8
unused(7:0)
Bit
7
6
5
4
3
2
1
0
WSel
0
SchedNo(5:0)
WSel
SCTI table entry Word Select
1
Selects the high word (bit 31..16) for next access via
register SCTIU/SCTID
0
Selects the low word (bit 15..0) for next access via
register SCTIU/SCTID
SchedNo(5:0)
Scheduler Number
Selects one of the 48 core-specific Schedulers for next access via
register SCTIU/SCTID. Only values in the range 0..47_D are valid.
Data Sheet
6-136
09.99