PXB4330 Datasheet, PDF (171/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register 60 TEST
TEST Register
Register Descriptions
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Read/Write
0000_H
TEST
F0_H
Written and Read by CPU for device test purposes
Bit
15
14
13
12
11
10
9
8
Unused(1:0)
CLKdelay(1:0)
BistRes(4:1)
Bit
7
6
5
4
3
2
1
0
BistRes0 StartBist
flags(5:0)
•
CLKDelay(1:0)
This bit-field adjusts the delay of TSTCLK output with respect to
SYSCLK input.
00
Delay 0
01
Delay 2
10
Delay 4
11
Delay 6
BistRes(4:0)
Result of BIST of internal RAMs.
After execution, all five bits must be zero; otherwise, an internal
RAM failure was detected.
StartBist
Starts internal RAM BIST
Automatically cleared after execution of the Bist procedure.
flags(5:0)
This bit-field controls special test modes.
It is recommended to Write all 0s to this bit-field.
Data Sheet
6-171
09.99