PXB4330 Datasheet, PDF (132/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Register Descriptions
Init(7:0)
Scheduler Initialization Value
This bit-field must be written to 00_H at the time of Scheduler
configuration/initialization and should not be written during normal
operation.
FracRate(7:0)
Fractional Rate
This value determines the fractional part of the Scheduler output
rate.
Note: Recommendation for changing the UTOPIA port number or scheduler rate
during operation:
Disable specific scheduler by read-modify-write operation to corresponding bit in
registers SCEN0U/SCEN0D... SCEN2U/SCEN2D.
Modify scheduler specific UTOPIA port number and rates via Table 7 "Scheduler
Configuration Table Integer Transfer Registers" on page 6-134, registers SCTIU/
SCTID and Table 6 "Scheduler Configuration Table Fractional Transfer
Registers" on page 6-130, registers SCTFU/SCTFD.
Enable specific scheduler by read-modify-write operation to corresponding bit in
registers SCEN0U/SCEN0D... SCEN2U/SCEN2D.
The following formulars explain how the two parameters IntRate and FracRate deter-
mine the scheduler output rate R via an auxiliary parameter T:
T=
------^S----^Y-----^S----^C-----^L----^K--------
32 cells^–1 × R
with
• ABM core clock, [SYSCLK} = 1/s
• Scheduler output rate, [R] = cells/s
[without dimension]
IntRate = int(T)
with
• int(T) is integer part of T
FracRate = {T – int(T)} × 256 + 1
Thus IntRate and FracRate can be calculated for a given scheduler output rate R.
Data Sheet
6-132
09.99