PXB4330 Datasheet, PDF (55/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Operational Description
6Mbps
6Mbps
ABM
#1
#2
6Mbps
#48
6Mbps
#49
6Mbps
#95
34Mbps
#96
Queue Traffic Class
1
CBR
2
GFR
3
GFR
4
UBR
:
:
5
6
CBR
GFR
upstream
7
GFR
ABM Core
8
UBR
:
:
:
189
CBR
190
GFR
191
GFR
192
UBR
193
CBR
194
GFR
195
GFR
196
UBR
:
:
:
377
CBR
378
GFR
379
GFR
downstream
380
UBR
ABM Core
400
CBR
401
UBR
402
GFR
:
:
591
GFR
The total rate of all Schedulers shouldn’t exceed 622 Mbit/s (payload rate)
QID = 0 is reserved for the queue for the common real time bypass !
Figure 4-3 ABM Configuration Example: DSLAM
4.6
Normal Operation
In normal operation, no microprocessor interaction is necessary as the ABM chip does
all queuing and scheduling automatically. For maintenance purposes, periodically the
microprocessor could read out the counters for buffer overflow events. Some overflow
events may also be programmed as interrupts.
The only instance of permanent microprocessor interaction is operation of the dynamic
bandwidth allocation protocol. In this case, the microprocessor must permanently check
the two fill thresholds of the upstream Schedulers and adjust their output rates
accordingly.
In case of static bandwidth allocation, all rate adjustments are made only at connection
setup or teardown.
Data Sheet
4-55
09.99