PXB4330 Datasheet, PDF (5/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
List of Figures
Page
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 1-5
Figure 1-6
Figure 1-7
Figure 1-8
Figure 1-9
Figure 1-10
Figure 2-1
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 3-10
Figure 4-1
Figure 4-2
Figure 4-3
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
ATM Switch Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
ABM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
ATM Switch Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Mini Switch with 622 Mbit/s Throughput . . . . . . . . . . . . . . . . . . . . . . 1-23
Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
ABM in Bi-directional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
ABM in Uni-directional Mode Using both Cores. . . . . . . . . . . . . . . . . 1-26
ABM in Uni-directional Mode Using one Core . . . . . . . . . . . . . . . . . . 1-27
Connection Identifiers in Mini-Switch Configuration. . . . . . . . . . . . . . 1-28
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Block Diagram of one ABM Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
ABM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
Scheduler Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Scheduler Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
Data Traffic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
Scheduler Behavior Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Scheduler Usage at Switch Output . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
Scheduler Usage at Switch Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
Queue Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Example of Threshold Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Parameters for Connection Setup (Bit width indicated) . . . . . . . . . . . 4-50
ABM Application Example: DSLAM . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
ABM Configuration Example: DSLAM . . . . . . . . . . . . . . . . . . . . . . . . 4-55
UTOPIA Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-63
Upstream Receive UTOPIA Example: 4 x 6 PHYs . . . . . . . . . . . . . . 5-66
SSRAM Interface Using 2 Mbit RAM . . . . . . . . . . . . . . . . . . . . . . . . . 5-69
SDRAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-70
Microprocessor Interface: Intel Mode. . . . . . . . . . . . . . . . . . . . . . . . . 5-71
Microprocessor Interface: Motorola Mode . . . . . . . . . . . . . . . . . . . . . 5-71
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-72
Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73
Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . 7-177
Microprocessor Interface Write Cycle Timing (Intel) . . . . . . . . . . . . 7-178
Microprocessor Interface Read Cycle Timing (Intel) . . . . . . . . . . . . 7-179
Microprocessor Interface Write Cycle Timing (Motorola) . . . . . . . . . 7-180
Microprocessor Interface Read Cycle Timing (Motorola). . . . . . . . . 7-182
Setup and Hold Time Definition (Single- and Multi-PHY). . . . . . . . . 7-184
Tristate Timing (Multi-PHY, Multiple Devices Only) . . . . . . . . . . . . . 7-185
SSRAM Interface Generic Timing Diagram . . . . . . . . . . . . . . . . . . . 7-189
Generic SDRAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . 7-190
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-192
Data Sheet
5
09.99