PXB4330 Datasheet, PDF (189/201 Pages) Infineon Technologies AG – ICs for Communications

PXB 4330
Electrical Characteristics
7.4.4 SSRAM Interface
Timing of the Synchronous Static RAM Interfaces is simplified as all signals are refer-
enced to the rising edge of SYSCLK. In Figure 7-8, it can be seen that all signals output
by the PXB 4330 E ABM have identical delay times with reference to the clock. When
reading from the RAM, the PXB 4330 E ABM samples the data within a window at the
rising clock edge.
SYSCLK
ADSC, ADV, A(17:0),
GE, CW, OW
RDATx(31:0), output
RDATx(31:0), input
100
101
102
103
104
105 106
Figure 7-8 SSRAM Interface Generic Timing Diagram
Table 7-13 SSRAM Interface AC Timing Characteristics
No. Parameter
Limit Values
Min
Typ
Max
100 T_SYSCLK : Period SYSCLK
19.3
100A F_SYSCLK : Frequency SYSCLK
52
101 SYSCLK Low Pulse Width
7.3
102 SYSCLK High Pulse Width
7.3
103 Delay SYSCLK rising to ADSC,
2
16
A(17:0), GW, CE, OE
104 Delay SYSCLK rising to RDATx Output 2
16
Unit
ns
MHz
ns
ns
ns
ns
Data Sheet
7-189
09.99