HD6437020 Datasheet, PDF (98/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

• Bits 3 and 2 (read/write select (RW1, RW0)): RW1, RW0 select whether to break on read
and/or write access cycles.
Bit 3: RW1
0
1
Bit 2: RW0
0
1
0
1
Description
No break interrupt occurs (initial value)
Break only on read cycles
Break only on write cycles
Break on both read and write cycles
• Bits 1 and 0 (operand size select (SZ1, SZ0)): SZ1, SZ0 select bus cycle operand size as a
break condition.
Bit 1: SZ1
Bit 0: SZ0
Description
0
0
Operand size is not a break condition (initial value)
1
Break on byte access
1
0
Break on word access
1
Break on long word access
Note:
When setting to break on an instruction fetch, set the SZ0 bit to 0. All instructions will be
considered to be accessed as words (even those instructions in on-chip memory for which
two instructions can be fetched simultaneously in a single bus cycle). Instruction fetch is by
word access and CPU/DMAC data access is by the specified operand size. They are not
determined by the bus width of the space being accessed.
6.3 Operation
6.3.1 Flow of the User Break Operation
The flow from setting of break conditions to user break interrupt exception processing is described
below.
1. Break conditions are set in break address register (BAR), break address mask register
(BAMR), and the break bus cycle register (BBR). Set the break address in the BAR, the
address bits to be masked in the BAMR and the type of breaking bus cycle in the BBR. When
even one of the BBR groups (CPU cycle/DMA cycle select bits (CD1, CD0), instruction
fetch/data access select bits (ID1, ID0), read/write select bits (RW1, RW0)) is set to 00 (no
user break interrupt), there will be no user break even when all other conditions are consistent.
To use a user break interrupt, set conditions for all three pairs.
2. The UBC checks to see if the set conditions are satisfied, using the system shown in figure 6.2.
When the break conditions are satisfied, the UBC sends a user break interrupt request to the
interrupt controller.
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