HD6437020 Datasheet, PDF (190/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3)
DMA transfer count registers 0-3 (TCR0–TCR3) are 16-bit read/write registers that specify the
DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001,
65535 when the setting is H'FFFF and 65536 (the maximum) when H'0000 is set. During a DMA
transfer, these registers indicate the remaining transfer count. The initial value after resets or in
standby mode is undefined.
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) are 16-bit read/write registers that control
the DMA transfer mode. They also indicate DMA transfer status. They are initialized to H'0000 by
a reset or standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
Bit name: AM
AL
DS
TM
TS
Initial value: 0
0
0
0
0
R/W: R/(W)^*2 R/(W)^*2 R/(W)^*2 R/W
R/W
Notes: 1. Write only 0 to clear the flag.
2. Writing is effective only for CHCR0 and CHCR1.
2
1
0
IE
TE
DE
0
0
0
R/W R/(W)* R/W
HITACHI 175