HD6437020 Datasheet, PDF (60/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 2.18 Operation Code Map (cont)
Instruction Code
Fx: 0000
Fx: 0001
MSB
LSB MD: 00
MD: 01
1100 00MD imm/disp MOV.B R0,@ MOV.W R0,@
(disp:8,GBR) (disp:8,GBR)
1100 01MD disp
MOV.B
@(disp:8,
GBR),R0
MOV.W
@(disp:8,
GBR),R0
1100 10MD imm TST
#imm:8,R0
AND
#imm:8,R0
1100 11MD imm TST.B
#imm:8,
@(R0,GBR)
AND.B
#imm:8,
@(R0,GBR)
1101 Rn
disp MOV.L @(disp:8,PC),Rn
1110 Rn
imm MOV #imm:8,Rn
1111
...
Fx: 0010
MD: 10
MOV.L R0,@
(disp:8,GBR)
MOV.L
@(disp:8,
GBR),R0
XOR
#imm:8,R0
XOR.B
#imm:8,
@(R0,GBR)
Fx: 0011–1111
MD: 11
TRAPA #imm:8
MOVA
@(disp:8,
PC),R0
OR
#imm:8,R0
OR.B
#imm:8,
@(R0,GBR)
2.5 CPU State
2.5.1 State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. The transitions between the states are shown in figure 2.6. For more information
on the reset and exception processing states, see section 4, Exception Processing. For details on
the power-down states, see section 19, Power Down States.
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