HD6437020 Datasheet, PDF (186/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

On-chip
ROM
On-chip
RAM
On-chip
peripheral
module
DREQ0, DREQ1
ITU
SCI
DACK0, DACK1
DEIn
External
ROM
External
RAM
External device
(memory
mapped)
External device
(with
acknowledge)
Iteration
control
Register
control
Start-up
control
Request
priority
control
Bus interface
Bus controller
DMAOR: DMA operation register
SARn: DMA source address register
DARn: DMA destination address register
TCRn: DMA transfer count register
CHCRn: DMA channel control register
DEIn: DMA transfer-end interrupt request to CPU.
n: 0–3
Figure 9.1 DMAC Block Diagram
SARn
DARn
TCRn
CHCRn
DMAOR
DMAC
HITACHI 171