HD6437020 Datasheet, PDF (169/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

8.6.2 Wait State Control
When the address/data multiplexed I/O space is accessed, the WAIT pin input signal is sampled
and a wait state inserted whenever a low level is detected, regardless of the setting of the WCR.
Figure 8.33 shows an example in which a WAIT signal causes a wait state of 1 state to be inserted.
CK
A21–A0
CS
AH
RD
Read
AD15–AD0
WRH, WRL
Write
AD15–AD0
WAIT
Tw
T1
T2
T3 (wait state)
T4
Address
Address
Data (input)
Data (output)
Figure 8.33 Wait State Timing For Address/Data Multiplexed I/O Space Access
8.6.3 Byte Access Control
The byte access control signals when the address/data multiplexed I/O space is being accessed are
of two types (WRH, WRL, A0, or WR, HBS, LBS), just as for byte access control of external
memory space access. These types can be selected using the BAS bit of the BCR. See section
8.4.3, Byte Access Control, for details.
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