HD6437020 Datasheet, PDF (157/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

T_p
T_r
T_c
CK
A21–A0
Row address Column address
RAS
Byte
control
CASH
CASL
WRH
WRL
High level
High level fixed
(a) Dual CAS signals (CW2 = 0)
T_p
T_r
T_c
CK
A21–A0
RAS
CASH
CASL
Byte
control
WRH
WRL
Row address Column address
High level fixed
High level
(a) Dual WE signals (CW2 = 1)
Figure 8.21 Byte Access Control Timing for DRAM Access (Upper Byte Write Cycle, Short
Pitch)
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