HD6437020 Datasheet, PDF (220/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

CK
DREQ
Bus
cycle
CPU
CPU
DMAC(R) DMAC(W) DMAC(R) DMAC(W)
CPU
DACK
Note: Dual address DREQ level detection, DACK active low, DACK output in read cycle, 1
bus cycle = 2 states.
Figure 9.24 DREQ Pin Sampling Timing in Burst Mode
9.3.6 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and all channels ending
together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel's DMA transfer count register (TCR) is 0, or when the DE bit of the
channel's CHCR is cleared to 0.
• When TCR is 0: When the TCR value becomes 0 and the corresponding channel’s DMA
transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt enable) bit
has been set, a DMAC interrupt (DEI) is requested to the CPU.
• When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR. The TE bit is not set when this happens.
Conditions for Ending All Channels Simultaneously: Transfers on all channels end when 1) the
NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or 2) when the
DME bit in the DMAOR is cleared to 0.
HITACHI 205