HD6437020 Datasheet, PDF (471/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

CK
A21–A0
HBS, LBS
CSn
RD
(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
WRH, WRL,
WR (Write)
AD15–AD0
DPH, DPL
(Write)
DACK0
DACK1
(Write)
WAIT
T₁
T_W
T₂
t_RDAC2*¹
t_ACC2*²
t_WTS t_WTH
t_WTS t_WTH
Notes: 1.
2.
For t_RDAC2, use t_cyc × (n + 1.65) – 20 (for 35% duty) or t_cyc × (n + 1.5) – 20 (for
50% duty) instead of t_cyc × (n + 2) – t_RDD – t_RDS.
For t_ACC2, use t_cyc × (n + 2) – 30 instead of t_cyc × (n + 2) – t_AD (or t_CSD1) – t_RDS.
Figure 19.10 Basic Bus Cycle: Two States + Wait State
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