HD6437020 Datasheet, PDF (368/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

13.2.8 Bit Rate Register (BRR)
The bit rate register (BRR) is an eight-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a reset or in
standby mode. SCI1 and SCI2 have independent baud rate generator control, so different values
can be set in the two channels.
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 13.3 shows examples of BRR settings in the asynchronous mode; table 13.4 shows
examples of BBR settings in the clocked synchronous mode.
Table 13.3 Bit Rates and BRR Settings in Asynchronous Mode
Bit Rate
(bits/s)
n
110
1
150
1
300
0
600
0
1200
0
2400
0
4800
0
9600
—
19200
—
31250
0
38400
—
2
N
141
103
207
103
51
25
12
—
—
1
—
φ (MHz)
Error (%)
n
0.03
1
0.16
1
0.16
0
0.16
0
0.16
0
0.16
0
0.16
0
—
0
—
—
0.00
—
—
—
2.097152
Error (%)
N
148
–0.04
108
0.21
217
0.21
108
0.21
54
–0.70
26
1.14
13
–2.48
6
–2.48
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—
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