HD6437020 Datasheet, PDF (468/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 19.7 Bus Timing (2) (cont)
Conditions: V_CC = 5.0 V ±10%, V_SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Item
Symbol Min Max
Unit Figures
DACK0, DACK1 delay time 1
DACK0, DACK1 delay time 2
DACK0, DACK1 delay time 3
t_DACD1
t_DACD2
t_DACD3
— 25
— 25
— 25
ns 19.8, 19.9, 19.11–19.14,
ns ^{19.19, 19.20}
ns 19.9, 19.13, 19.14,
19.19
DACK0, DACK1 delay time 4
DACK0, DACK1 delay time 5
Read delay
time
35% duty^*2
50% duty
Data setup time for CAS
CAS setup time for RAS
Row address hold time
Write command hold time
Write command 35% duty^*2
setup time
50% duty
t_DACD4
t_DACD5
t_RDD
t_DS
t_CSR
t_RAH
t_WCH
t_WCS
— 25
ns
— 25
ns
— t_cyc × 0.35 + 12 ns
— t_cyc × 0.5 + 15 ns
0^*5 —
ns
10 —
ns
10 —
ns
15 —
ns
0—
ns
0—
ns
19.11, 19.12
19.8, 19.9, 19.11-19.15,
19.19
19.11, 19.13
19.16, 19.17, 19.18
19.11, 19.13
19.11
Access time from CAS
precharge^*6
t_ACP
t_cyc —
−20
ns 19.12
Notes 1. HBS and LBS signals are 30 ns.
2. When frequency is 10 MHz or more
3. n is the number of wait cycles.
4. Access time from addresses A0 to A21 is tcyc-25.
5. –5 ns for parity output of DRAM long-pitch access
6. It is not necessary to meet the t_RDS specification as long as the access time
specification is met.
HITACHI 460