HD6437020 Datasheet, PDF (164/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

CK
A21–
A0
RAS
CAS
AD15–
AD0
DRAM access
External memory
space access _{DRAM access}
T_p
T_r
T_c
T_c
T1
T_p
T_r
T_c
Column Column External memory
address 1 address 2
address
Column
address 3
Row address
Row address
Data 1 Data 2
External
memory data
Figure 8.28 RAS Up Mode
Data 3
8.5.6 Refresh Control
The BSC has a function for controlling DRAM refreshing. By setting the refresh mode bit
(RMODE) in the refresh control register (RCR), either CAS-before-RAS refresh (CBR) or self-
refresh can be selected. When no refresh is performed, the refresh timer counter (RTCNT) can be
used as an 8-bit interval timer.
CAS-Before-RAS Refresh (CBR): A refresh is performed at an interval determined by the input
clock selected in the clock select bits 2–0 (CKS2–CKS0) of the refresh timer control/status
register (RTCSR) and the value set in the refresh time constant register (RTCOR). Set the values
of RTCOR and CKS2–CKS0 so they satisfy the refresh interval specifications of the DRAM being
used.
To perform a CBR refresh, clear the RMODE bit of the RCR to 0 and then set the refresh control
bit (RFSHE) bit to 1. Also write in the required values to RTCNT and RTCOR. When the clock is
thereafter selected in the CKS2–CKS0 bits of the RTCSR, the RTCNT will begin to increment
from its current value. The RTCNT value is constantly compared to the RTCOR value and the
CBR refresh is performed when they match. The RTCNT is simultaneously cleared to H'00 and
incrementing begins again.
When the clock is selected in the CKS2–CKS0 bits, the RTCNT immediately begins to increment
from its current value. This means that when the RTCOR cycle is set after the CKS2–CKS0 bits
are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the
RTCNT will overflow once (H'FF goes to H'00) and incrementing will start again. Since the CBR
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