HD6437020 Datasheet, PDF (89/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

5.4.2 Stack after Interrupt Exception Processing
Figure 5.3 shows the stack after interrupt exception processing.
Address
4n–8
4n–6
4n–4
4n–2
4n
PC*²
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
SP*³
Notes: 1.
2.
3.
Bus width is 16 bits.
PC stores the top address of the next instruction (return instruction) after the
executed instruction.
The value of SP must always be a multiple of four.
Figure 5.3 Stack after Interrupt Exception Processing
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