HD6437020 Datasheet, PDF (168/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

8.6.1 Basic Timing
When the multiplexed I/O enable bit (IOE) of the BCR is set to 1, the area 6 space with address bit
A27 as 0 (H'6000000–H'6FFFFFF) becomes an address/data multiplexed I/O space that, when
accessed, multiplexes addresses and data. When the A14 address bit is 0, the bus width is 8 bits
and address output and data input/output are performed from the AD7–AD0 pins. When the A14
address bit is 1, the bus width is 16 bits and address output and data input/output are performed
from the AD15–AD0 pins. In the address/data multiplexed I/O space, access is controlled with the
AH, RD and WR signals. Accesses in the address/data multiplexed I/O space is performed in 4
states, regardless of the WCR settings. Figure 8.32 shows the timing when the address/data
multiplexed I/O space is accessed.
CK
A21–A0
CS
AH
RD
Read
AD15–AD0
WRH, WRL
Write
AD15–AD0
T1
T2
Address
Address
T3
T4
Data (input)
Data (output)
Figure 8.32 Access Timing For Address/Data Multiplexed I/O Space
The high-level duty of the RD signal can be selected between 35% and 50% using the RD duty bit
(RDDTY) of the BCR. When RDDTY is 1, the high-level duty is 35% of the T3 or Tw state,
lengthening the access time for external devices.
152 HITACHI