HD6437020 Datasheet, PDF (56/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 2.17 System Control Instructions
Instruction
Instruction Code Operation
Execution T bit
Cycles
CLRT
0000000000001000 0 → T
1
0
CLRMAC
0000000000101000 0 → MACH, MACL
1
—
LDC Rm,SR
0100mmmm00001110 Rm → SR
1
LSB
LDC Rm,GBR
0100mmmm00011110 Rm → GBR
1
—
LDC Rm,VBR
0100mmmm00101110 Rm → VBR
1
—
LDC.L @Rm+,SR
0100mmmm00000111 (Rm) → SR, Rm + 4 → Rm 3
LSB
LDC.L @Rm+,GBR
0100mmmm00010111 (Rm) → GBR, Rm + 4 → Rm 3
—
LDC.L @Rm+,VBR
0100mmmm00100111 (Rm) → VBR, Rm + 4 → Rm 3
—
LDS Rm,MACH
0100mmmm00001010 Rm → MACH
1
—
LDS Rm,MACL
0100mmmm00011010 Rm → MACL
1
—
LDS Rm,PR
0100mmmm00101010 Rm → PR
1
—
LDS.L @Rm+,MACH 0100mmmm00000110 (Rm) → MACH, Rm + 4 → 1
—
Rm
LDS.L @Rm+,MACL 0100mmmm00010110 (Rm) → MACL, Rm + 4 → 1
—
Rm
LDS.L @Rm+,PR
0100mmmm00100110 (Rm) → PR, Rm + 4 → Rm 1
—
NOP
0000000000001001 No operation
1
—
RTE
0000000000101011 Delayed branch, stack area 4
—
→ PC/SR
SETT
0000000000011000 1 → T
1
1
SLEEP
0000000000011011 Sleep
3*
—
STC SR,Rn
0000nnnn00000010 SR → Rn
1
—
STC GBR,Rn
0000nnnn00010010 GBR → Rn
1
—
STC VBR,Rn
0000nnnn00100010 VBR → Rn
1
—
STC.L SR,@–Rn
0100nnnn00000011 Rn–4 → Rn, SR → (Rn)
2
—
STC.L GBR,@–Rn
0100nnnn00010011 Rn–4 → Rn, GBR → (Rn)
2
—
STC.L VBR,@–Rn
0100nnnn00100011 Rn–4 → Rn, VBR → (Rn)
2
—
STS MACH,Rn
0000nnnn00001010 MACH → Rn
1
—
STS MACL,Rn
0000nnnn00011010 MACL → Rn
1
—
STS RR,Rn
0000nnnn00101010 PR → Rn
1
—
Note: The number of execution states before the chip enters the sleep state.
HITACHI 37