HD6437020 Datasheet, PDF (120/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Bit 15: WPU
0
1
Description
WAIT pin is not pulled up
WAIT pin is pulled up (initial value)
• Bits 14 and 13 (long wait insertion in areas 0 and 2, bits 1, 0 (A02LW1 and A02LW0)):
A02LW1 and A02LW0 select the long wait states to be inserted (1–4 states) when accessing
external memory space of areas 0 and 2.
Bit 14: A02LW1 Bit 13: A02LW0 Description
0
0
Inserts 1 state
1
Inserts 2 states
1
0
Inserts 3 states
1
Inserts 4 states (initial value)
• Bits 12 and 11 (long wait insertion in area 6, bits 1, 0 (A6LW1 and A6LW0)): A6LW1 and
A6LW0 select the long wait states to be inserted (1–4 states) when accessing external memory
space of area 6.
Bit 12: A6LW1
0
1
Bit 11: A6LW0
0
1
0
1
Description
Inserts 1 state
Inserts 2 states
Inserts 3 states
Inserts 4 states (initial value)
• Bits 10–0 (reserved): These bits always read as 0. The write value should always be 0.
8.2.5 DRAM Area Control Register (DCR)
The DRAM area control register (DCR) is a 16-bit read/write register that selects the type of
DRAM control signal, the number of precharge cycles, the burst operation mode and the use of
address multiplexing. DCR settings are valid only when the DRAME bit of BCR is set to 1. It is
initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby
mode.
104 HITACHI