HD6437020 Datasheet, PDF (210/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Transfer requests can be auto requests, external requests, or on-chip peripheral module
requests. When the transfer request source is either the SCI or A/D converter, however, either
the data destination or source must be the SCI or A/D converter (figure 9.4), In dual address
mode, DACK is output in read or write cycles to onchip memory or onchip peripheral
modules. The CHCR controls the cycle of DACK output.
Figure 9.9 shows the DMA transfer timing in the dual address mode.
CK
A21–A0
CSn
D15–D0
RD
WRH
WRL
DACK
Source address Destination address
Figure 9.9 DMA Transfer Timing in the Dual Address Mode (External memory space to
external memory space transfer with DACK output in the read cycle)
Bus Modes: There are two bus modes: cycle steal and burst. Select the mode in the TM bits of
CHCR0–CHCR3.
• Cycle-Steal Mode
In the cycle steal mode, the bus right is given to another bus master after a one-transfer-unit
(word or byte) DMA transfer. When another transfer request occurs, the bus rights are obtained
from the other bus master and a transfer is performed for one transfer unit. When that transfer
ends, the bus right is passed to the other bus master. This is repeated until the transfer end
conditions are satisfied.
The cycle steal mode can be used with all categories of transfer destination, transfer source and
transfer request. Figure 9.10 shows an example of DMA transfer timing in the cycle steal
mode. Transfer conditions shown in the figure are:
 Dual address mode
 DREQ level detection
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