HD6437020 Datasheet, PDF (170/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

8.7 Parity Check and Generation
The BSC can check and generate parity for data input and output to or from in the DRAM space of
area 1 and the external memory space of area 2.
To check and generate parity, select the space (DRAM space only, or DRAM space and area 2) for
which parity is to be checked and generated using the parity check enable bits (PCHK1 and
PCHK0) of the parity control register and select odd or even parity in the parity polarity bit (PEO).
When data is input from the space selected in the PCHK1 and PCHK0 bits, the BSC checks the
PEO bit to see if the polarity of the DPH pin input (upper byte parity data) is accurate for the
AD15–AD8 pin input (upper byte data) or if the DPL pin input (lower byte parity data) is accurate
for the AD7–AD0 pin input (lower byte data). If the check indicates that either the upper or lower
byte parity is incorrect, a parity error interrupt is produced (PEI).
When outputting data to the space selected in the PCHK1 and PCHK0 bits, the BSC outputs parity
data output of the polarity set in the PEO bit from the DPH pin for the AD15–AD8 pin output
(upper byte data) or from the DPL pin for the AD7–AD0 pin input (lower byte data) using the
same timing as the data output.
The BSC is also able to force a parity output for use in testing the system’s parity error check
function. When the parity force output bit (PFRC) of the PCR is set to 1, a high level is forcibly
output from the DPH and DPL pins when data is output to the space selected in the PCHK1 and
PCHK0 bits.
8.8 Warp Mode
In warp mode, an external write cycle or DMA single address mode transfer cycle and an internal
access cycle (read/write to on-chip memory or on-chip peripheral modules) operate independently
in parallel. The warp mode is entered by setting the warp mode bit (WARP) in the BCR to 1. This
allows the LSI to be operated at high speed.
When in the warp mode an external write cycle or DMA single address mode transfer cycle
continues for at least 2 states and their is an internal access, only the external write cycle will be
performed in the initial state. The external write cycle and internal access cycle will be performed
in parallel from the next state on, without waiting for the end of the external write cycle. Figure
8.34 shows the timing when an access to an on-chip peripheral module and an external write cycle
are performed in parallel.
154 HITACHI