HD6437020 Datasheet, PDF (410/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

• When using an external clock source for the serial clock, update the TDR with the DMAC, and
then after five system clocks or more elapse, input a transmit clock. If a transmit clock is input
in the first four system clocks after the TDR is written, an error may occur (figure 13.22).
• Before reading the receive data register (RDR) with the DMAC, select the receive-data-full
interrupt of the SCI as a start-up source using the resource select bit (RS) in the channel control
register (CHCR).
SCK
t
TDRE
D0
D1
D2
D3
D4
D5
D6
D7
Note: During external clock operation, an error may occur if t is 4φ or less.
Figure 13.22 Clocked Synchronous Transmitting Example with DMAC
Cautions for Clocked Synchronous External Clock Mode:
• Set TE = RE = 1 only when the external clock SCI is 1.
• Do not set TE = RE = 1 until at least 4 clocks after the external clock SCK has changed from 0
to 1.
• When receiving, RDRF = 1 when RE is set to zero 2.5–3.5 clocks after the rise edge of the
RxD D7 bit SCK input, but it cannot be copied to RDR.
Caution for Clocked Synchronous Internal Clock Mode: When receiving, RDRF = 1 when RE
is set to zero 1.5 clocks after the rise edge of the RxD D7 bit SCK input, but it cannot be copied to
RDR.
HITACHI 397