HD6437020 Datasheet, PDF (459/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

19.3.2 Control Signal Timing
Table 19.5 Control Signal Timing
Case A: V_CC = 3.0 to 5.5 V, V_SS = 0 V, Ta = –20 to +75°C*
Case B: V_CC = 5.0 V ±10%, V_SS = 0 V, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Case A
Case B
12.5 MHz 16.6 MHz 20 MHz
Item
Symbol Min Max Min Max Min Max Unit Figure
RES setup time
t_RESS 320 —
RES pulse width
t_RESW 20
—
NMI reset setup time
t_NMIRS 320 —
NMI reset hold time
t_NMIRH 320 —
NMI setup time
t_NMIS 160 —
NMI hold time
t_NMIH
80
—
IRQ0–IRQ7 setup time (edge t_IRQES 160 —
detection time)
240 —
20 —
240 —
240 —
120 —
60 —
120 —
200 —
20 —
200 —
200 —
100 —
50 —
100 —
ns 19.4
t_cyc
ns
ns
ns 19.5
ns
ns
IRQ0–IRQ7 setup time (level t_IRQLS 160 — 120 — 100 — ns
detection time)
IRQ0–IRQ7 hold time
t_IRQEH 80
IRQOUT output delay time)
t_IRQOD —
Bus request setup time
t_BRQS 80
Bus acknowledge delay time 1 t_BACD1 —
Bus acknowledge delay time 2 t_BACD2 —
Bus 3-state delay time
t_BZD
—
— 60 — 50 — ns
80 — 60 — 50 ns 19.6
— 60 — 50 — ns 19.7
80 — 60 — 50 ns
80 — 60 — 50 ns
80 — 60 — 50 ns
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