HD6437020 Datasheet, PDF (340/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

When a compare match B occurs before the compare match A, the 0 data transfer can be
performed before the 1 data transfer, so a non-overlapping waveform can be output. In such cases,
be sure not to change the NDR contents until the compare match A after the compare match B
occurs (non-overlap period). This can be ensured by writing the next data to the NDR using the
IMIA interrupt service routine. The DMAC can also be started up using an IMIA interrupt.
However, these write operations should be performed prior to the next compare match B. The
timing is shown in figure 11.10.
Compare
match A
Compare
match B
NDR
NDR write
NDR write
DR
0 output 0/1 output
0 output 0/1 output
NDR write period
NDR write period
NDR write
disable period
NDR write
disable period
Figure 11.10 Non-Overlap Operation and NDR Write Timing
326 HITACHI