HD6437020 Datasheet, PDF (367/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

• Bit 2 (transmit end (TEND)): TEND indicates that when the last bit of a serial character was
transmitted, the TDR did not contain new transmit data, so transmission has ended. TEND is a
read-only bit and cannot be written.
Bit 2: TEND
0
1
Description
Transmission is in progress
TEND is cleared to 0 when:
• Software reads TDRE after it has been set to 1, then writing 0 in TDRE
• The DMAC writes data in TDR
End of transmission (initial value)
TEND is set to 1 when:
• The chip is reset or enters standby mode
• TE is cleared to 0 in the serial control register (SCR)
• TDRE is 1 when the last bit of a one-byte serial character is transmitted
• Bit 1 (multiprocessor bit (MPB)): MPB stores the value of the multiprocessor bit in receive
data when a multiprocessor format is selected for receiving in the asynchronous mode. The
MPB is a read-only bit and cannot be written.
Bit 1: MPB
0
1
Description
Multiprocessor bit value in receive data is 0. If RE is cleared to 0 when a
multiprocessor format is selected, the MPB retains its previous value (initial
value).
Multiprocessor bit value in receive data is 1
• Bit 0 (multiprocessor bit transfer (MPBT)): MPBT stores the value of the multiprocessor bit
added to transmit data when a multiprocessor format is selected for transmitting in the
asynchronous mode. The MPBT setting is ignored in the clocked synchronous mode, when a
multiprocessor format is not selected, or when the SCI is not transmitting.
Bit 0: MPBT
0
1
Description
Multiprocessor bit value in transmit data is 0 (initial value)
Multiprocessor bit value in transmit data is 1
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