HD6437020 Datasheet, PDF (163/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

CK
A21–
A0
RAS
CAS
WR
AD15–
AD0
DRAM access
External memory
space access _{DRAM access}
T_p
Tr
T_c
T_c
T1
T_c
T_c
Column Column External Column Column
address 1 address 2 memory address 3 address 4
Row address
Data 1
Data 2
External
memory data
Data 3
Data 4
Figure 8.27 RAS Down Mode
• RAS Up Mode: When the RASD bit is cleared to 0, the RAS signal reverts to high whenever a
DRAM access pauses for access to another space. Burst operation continues only while
DRAM access is continuous. Figure 8.28 shows the timing when an external memory space
access occurs during burst operation in the RAS up mode.
HITACHI 147