HD6437020 Datasheet, PDF (217/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Tp Tr Tc Tc
Tp Tr Tc Tc
CK
DREQ
Bus cycle _{CPU CPU CPU}
DMAC
CPU
DMAC
CPU
DACK
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer
will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.19 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Single address mode, bus cycle = DRAM bus cycle (long
pitch normal mode))
Tp Tr Tc Tc
Tp Tr Tc Tc
CK
DREQ
Bus cycle
CPU CPU CPU
DMAC(R)
DMAC
(W)
CPU
DMAC (R)
DMAC
(W)
CPU
DACK
Note:
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
When DREQ is negated at the fourth state of the DMAC cycle, the next DMA transfer
will be executed because the sampling is done at the second state of the DMAC cycle.
Figure 9.20 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Dual address mode, bus cycle = DRAM bus cycle (long
pitch normal mode))
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