HD6437020 Datasheet, PDF (245/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

• Bit 2 (buffer mode A4 (BFA4)): BFA4 selects the buffer mode for GRA4 and BRA4 in
channel 4.
Bit 2: BFA4
0
1
Description
GRA4 operates normally in channel 4 (initial value)
GRA4 and BRA4 operate in buffer mode in channel 4
• Bit 1 (buffer mode B3 (BFB3)): BFB3 selects the buffer mode for GRB3 and BRB3 in channel
3.
Bit 1: BFB3
0
1
Description
GRB3 operates normally in channel 3 (initial value)
GRB3 and BRB3 operate in buffer mode in channel 3
• Bit 0 (buffer Mode A3 (BFA3)): BFA3 selects the buffer mode for GRA3 and BRA3 in
channel 3.
Bit 0: BFA3
0
1
Description
GRA3 operates normally in channel 3 (initial value)
GRA3 and BRA3 operate in buffer mode in channel 3
10.2.5 Timer Output Control Register (TOCR)
The timer output control register (TOCR) is an eight-bit read/write register that inverts the output
level of the complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and
OLS4 is valid in only the complementary PWM mode and reset-synchronized PWM mode. In
other output situations, these bits are ignored. The TOCR is initialized to H'FF or H'7F by a reset
or in the standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
OLS4 OLS3
Initial value:
*
1
1
1
1
1
1
1
R/W: —
—
—
—
—
—
R/W R/W
Note: Undefined
• Bits 7–2 (reserved): Bit 7 is read as undefined. Bits 6–2 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–2 should always be 1.
HITACHI 231