HD6437020 Datasheet, PDF (145/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

T1
T2
CK
A21–A0
CSn
RD
Read
AD15–AD0
When
RDDTY = 0
When
RDDTY = 1
WRH, WRL
Write
AD15–AD0
Figure 8.12 Basic Timing of External Memory Space Access (2-state read timing)
High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit
(RDDTY) of the BCR. When RDDTY is set to 1, the high-level duty is 35% of the T1 state,
enabling longer access times for external devices. Only set to 1 when the operating frequency is a
minimum of 10 MHz.
8.4.2 Wait State Control
The number of external memory space access states and the insertion of wait states can be
controlled using the WCR1–WCR3 bits. The bus cycles that can be controlled are the CPU read
cycle and the DMAC dual mode read cycle. The bus cycle that can be controlled using the WCR2
is the DMAC single-mode read/write cycle.
Table 8.8 shows the number of states and number of wait states in the access cycles to external
memory spaces.
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