HD6437020 Datasheet, PDF (125/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name: CMF CMIE CKS2 CKS1 CKS0
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
—
—
—
• Bits 15–8 (reserved): These bits always read as 0.
• Bit 7 (compare match flag (CMF)): CMF is a flag that indicates whether the values of RTCNT
and the refresh time constant register (RTCOR) match. When 0, the value of RTCNT and
RTCOR do not match; when 1, the value of RTCNT and RTCOR match.
Bit 7: CMF
0
1
Description
RTCNT does not equal the value of RTCOR (initial value)
To clear CMF, the CPU must read CMF after it has been set to 1, then write a
0 in this bit
Value RTCNT is equal to the value of RTCOR
• Bit 6 (compare match interrupt enable (CMIE)): CMIE enables or disables the compare match
interrupt (CMI) generated when CMF is set to 1 in RTCSR (RTCNT value = RTCOR value).
When cleared to 0, CMI interrupt is disabled; when set to 1, it is enabled.
Bit 6: CMIE
0
1
Description
Compare match interrupt request (CMI) is disabled (initial value)
Compare match interrupt request (CMI) is enabled
• Bits 5–3 (clock select bits 2–0 (CKS2–CKS0)): CKS2–CKS0 select the clock input to RTCNT
from among the seven types of clocks created by dividing the system clock (φ). When the input
clock is selected with the CKS2–CKS0 bits, RTCNT starts to increment.
HITACHI 109