HD6437020 Datasheet, PDF (284/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1
for underflows only. The buffer register (BR) set for the buffer operation is transferred to the GR
upon compare match A3 (when incrementing) or TCNT4 underflow.
GR Setting in Complementary Mode: Be aware of the following when setting the general
registers in complementary PWM mode and when making changes during operation.
• Initial values: Setting H'0000 to T–1 (the initial setting T: TCNT3) is prohibited. After
counting starts, this setting is allowed from the point when the first A3 compare match occurs.
• Methods of changing settings: Use the buffer operation. Writing directly to general registers
may result in incorrect waveform output.
• When changing settings: See figure 10.38.
GRA3
GR
H' 0000
BR
GR
Prohibited
Figure 10.38 Example of Changing GR Settings with Buffer Operation (1)
270 HITACHI