English
Language : 

HD6437020 Datasheet, PDF (482/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine
Table 19.8 Bus Timing (3)
Conditions: VCC = 3.0 to 5.5 V, VSS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Item
Symbol Min
Max Unit Figures
Address delay time
tAD
—
40 ns 19.21, 19.22, 19.24–
19.27, 19.32, 19.33
CS delay time 1
tCSD1 —
40 ns 19.21, 19.22, 19.33
CS delay time 2
tCSD2 —
40 ns
CS delay time 3
tCSD3 —
40 ns 19.32
CS delay time 4
Access time 1*4 35% duty*1
from read strobe 50% duty
tCSD4
tRDAC1
—
tcyc × 0.65 – 35
tcyc × 0.5 – 35
40 ns
— ns 19.21,
— ns
Access time 2*4 35% duty*1 tRDAC2
from read strobe 50% duty
Access time 3*4 35% duty*1 tRDAC3
from read strobe 50% duty
tcyc × (n+1.65) – 35*2 —
tcyc × (n+1.5) – 35*2 —
tcyc × (n+0.65) – 35*2 —
tcyc × (n+0.5) – 35*2 —
ns 19.22, 19.23
ns
ns 19.32
ns
Read strobe delay time
tRSD
—
40 ns 19.21, 19.22, 19.32
Read data set-up time
tRDS
30
— ns 19.21, 19.22,
Read data hold time
tRDH
0
— ns 19.24-19.27, 19.32
Write strobe delay time 1
tWSD1 —
40 ns 19.22, 19.26, 19.27,
19.32, 19.33
Write strobe delay time 2
tWSD2 —
30 ns 19.22, 19.26, 19.27,
19.32
Write strobe delay time 3
Write strobe delay time 4
Write data delay time 1
tWSD3 —
tWSD4 —
tWDD1 —
40 ns 19.24, 19.25
40 ns 19.24, 19.25, 19.33
70 ns 19.22, 19.26, 19.27,
19.32
Write data delay time 2
Write data hold time
tWDD2 —
tWDH –10
40 ns 19.24, 19.25
— ns 19.22, 19.24–19.27,
19.32
Parity output delay time 1
Parity output delay time 2
Parity output hold time
tWPDD1 —
tWPDD2 —
tWPDH –10
80 ns 19.22, 19.24, 19.27
40 ns 19.24, 19.25
— ns 19.22, 19.24–19.27
HITACHI 474