HD6437020 Datasheet, PDF (257/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Internal data bus
H
CPU _L
Bus
interface
H
Module
L
data bus
TCNTH
TCNTL
Figure 10.9 Accessing TCNT (CPU–TCNT (lower byte))
Internal data bus
H
CPU _L
Bus
interface
H
Module
L
data bus
TCNTH
TCNTL
Figure 10.10 Accessing TCNT (TCNT–CPU (upper byte))
Internal data bus
H
CPU _L
Bus
interface
H
Module
L
data bus
TCNTH
TCNTL
Figure 10.11 Accessing TCNT (TCNT–CPU (lower byte))
10.3.2 8-Bit Accessible Registers
All registers other than the TCNT, general registers, and buffer registers are 8-bit registers. These
are connected to the CPU by an 8-bit data bus. Figures 10.12 and 10.13 illustrate reading and
writing in byte units with the timer control register (TCR). These registers must be accessed by
byte access.
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