HD6437020 Datasheet, PDF (303/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

10.6.5 Contention between TCNT Write and Overflow/Underflow
If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority over counter
incrementing. The OVF is set to 1. The same applies to underflows. This timing is shown in figure
10.62.
CK
Address
Internal
write signal
TCNT
input clock
Overflow
signal
TCNT
OVF
TCNT write cycle
T1
T2
T3
TCNT address
H'FFFF
M
TCNT write data
Figure 10.62 Contention between TCNT Write and Overflow
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