HD6437020 Datasheet, PDF (320/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

11.1.4 Registers
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Name
Abbreviation R/W
Initial
Value Address*¹
Access
Size`
Port B control register 1
PBCR1
R/W
H'0000 H'5FFFFCC
8, 16
Port B control register 2
PBCR2
R/W H'0000 H'5FFFFCE
8, 16
Port B data register
PBDR
R/(W)*² H'0000 H'5FFFFC2
8, 16
TPC output mode register
TPMR
R/W H'F0 H'5FFFFF0
8, 16
TPC output control register TPCR
R/W H'FF H'5FFFFF1
8, 16
Next data enable register B NDERB
R/W H'00 H'5FFFFF2
8, 16
Next data enable register A NDERA
R/W H'00 H'5FFFFF3
8, 16
Next data register A
NDRA
R/W
H'00 H'5FFFFF5/
8, 16
H'5FFFFF7*³
Next data register B
NDRB
R/W
H'00 H'5FFFFF4/
8, 16
H'5FFFFF6*³
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Description of Areas.
2. Bits used for TPC output cannot be written to.
3. These addresses change depending on TPCR settings. When TPC output groups 0
and 1 have the same output trigger, the NDRA address is H'5FFFFF5; when their
output triggers are different, the NDRA address for group 0 is H'5FFFFF7 and the
address for group 1 is H'5FFFFF5. Likewise, when TPC output groups 2 and 3 have the
same output trigger, the NDRB address is H'5FFFFF4; when their output triggers are
different, the NDRB address for group 0 is H'5FFFFF6 and the address for group 1 is
H'5FFFFF4.
11.2 Register Descriptions
11.2.1 Port B Control Registers 1 and 2 (PBCR1, PCBR2)
The port B control register 1 and 2 (PBCR1 and PBCR2) are 16-bit read/write registers that set the
functions of port B pins. Port B consists of the dual use pins TP15–TP0. Bits corresponding to the
pins to be used for TPC output must be set to 1. For details, see the port B description in the
section 15, Pin Function Controller.
306 HITACHI