HD6437020 Datasheet, PDF (302/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

10.6.4 Contention between GR Write and Compare Match
If a compare match occurs in the T3 state of a general register (GR) write cycle, writing takes
priority and the compare match signal is inhibited. The timing is shown in figure 10.61.
GR write cycle
T1
T2
T3
CK
Address
Internal
write signal
TCNT
GR address
N
N+1
GR
Compare
match signal
N
M
GR write data
Inhibited
Figure 10.61 Contention between General Register Write and Compare Match
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