HD6437020 Datasheet, PDF (467/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 19.7 Bus Timing (2) (cont)
Conditions: V_CC = 5.0 V ±10%, V_SS = 0 V, φ = 16.6 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Item
Symbol Min
Max Unit Figures
Wait setup time
Wait hold time
Read data access time 1^*6
Read data access time 2^*6
t_WTS
t_WTH
t_ACC1
t_ACC2
19
—
10
—
t_cyc – 30*⁴
—
t_cyc × (n+2) – —
30^*3
ns 19.10, 19.15, 19.19
ns
ns 19.8, 19.11, 19.12
ns 19.9, 19.10, 19.13,
19.14
RAS delay time 1
RAS delay time 2
t_RASD1 —
t_RASD2 —
25 ns 19.11–19.14,
35 ns ^{19.16–19.18}
CAS delay time 1
t_CASD1 —
25 ns 19.11
CAS delay time 2
CAS delay time 3
t_CASD2 —
t_CASD3 —
25 ns 19.13, 19.14,
25 ns ^{19.16–19.18}
Column address setup time
t_ASC
0
— ns 19.11, 19.12
Read data access 35% duty^*2 t_CAC1
time from CAS 1^*6
t_cyc × 0.65 – — ns
19
50% duty
Read data access time from
CAS 2^*6
t_CAC2
t_cyc × 0.5 – 19 —
t_cyc × (n + 1) – —
25^*3
ns
ns 19.13, 19.14, 19.15
Read data access time from
RAS 1^*6
t_RAC1
t_cyc × 1.5 – 20 — ns 19.11, 19.12
Read data access time from
RAS 2^*6
t_RAC2
t_cyc × (n + 2.5) —
– 20^*3
ns 19.13, 19.14, 19.15
High-speed page mode CAS t_CP
precharge time
t_cyc × 0.25
— ns 19.12
AH delay time 1
t_AHD1
—
AH delay time 2
t_AHD2
—
Multiplexed address delay time t_MAD
—
Multiplexed address hold time t_MAH
0
25 ns 19.19
25 ns
30 ns
— ns
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