HD6437020 Datasheet, PDF (253/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

10.2.11 Timer Status Register (TSR)
The timer status register (TSR) is an eight-bit read/write register containing flags that indicate
timer counter (TCNT) overflow/underflow and general register (GRA/GRB) compare match or
input capture. These flags are interrupt sources. If the interrupt is enabled by the corresponding bit
in the timer interrupt enable register (TIER), an interrupt is requested of the CPU. TSR is
initialized by a reset or standby mode to H'F8 or H'78. Each ITU channel has one TSR (table
10.9).
Table 10.9 Timer Status Register (TSR)
Channel
0
1
2
3
4
Abbreviation
TSR0
TSR1
TSR2
TSR3
TSR4
Function
The TSR indicates input capture, compare match and
overflow status.
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
OVF IMFB IMFA
Initial value: *¹
1
1
1
1
0
0
0
R/W: —
—
—
—
— R/(W)*² R/(W)*² R/(W)*²
Notes: 1. Undefined
2. Write 0 to clear the flag.
• Bits 7–3 (reserved): Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value
to bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
• Bit 2 (overflow flag (OVF)): OVF indicates a TCNT overflow/underflow has occurred.
Bit 2: OVF
Description
0
Clearing condition: Read OVF when OVF = 1, then write 0 in OVF
(initial value)
1
Setting condition: TCNT overflowed from H'FFFF–H'0000 or
underflowed from H'0000–H'FFFF.
Note:
A TCNT underflow occurs when the TCNT up/down counter is functioning. It may occur in
the following cases: (1) When channel 2 is set in the phase counting mode (MDF bit of
TMDR is 1), or (2) When channel 3 and 4 are set to the complementary PWM mode (CMD1
bit of TFCR is 1 and CMD0 bit is 0).
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