HD6437020 Datasheet, PDF (132/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 8.6 How Space is Divided
Area Address
Assign-able Memory
Capacity
Bus CS
(linear space) Width Output
0 H'0000000 – H'0FFFFFF On-chip ROM*¹
16 kB*³
32 kB*⁴
32
—
External memory*²
4 MB
8/16*⁵ CS0
1 H'1000000 – H'1FFFFFF External memory
4 MB
8
CS1
DRAM*⁶
16 MB
8
RAS CAS
2 H'2000000 – H'2FFFFFF External memory
4 MB
8
CS2
3 H'3000000 – H'3FFFFFF External memory
4 MB
8
CS3
4 H'4000000 – H'4FFFFFF External memory
4 MB
8
CS4
5 H'5000000 – H'5FFFFFF On-chip peripheral module 512 B
8/16*⁷ —
6 H'6000000 – H'6FFFFFF External memory*⁹
4 MB
8/16*⁸ CS6
Multiplexed I/O
4 MB
7 H'7000000 – H'7FFFFFF External memory
4 MB
8
CS7
0 H'8000000 – H'8FFFFFF On-chip ROM*¹
16 kB*³
32 kB*⁴
32
—
External memory*²
4 MB
8/16*⁵ CS0
1 H'9000000 – H'9FFFFFF External memory
4 MB
16
CS1
DRAM*⁶
16 MB
16
RAS CAS
2 H'A000000 – H'AFFFFFF External memory
4 MB
16
CS2
3 H'B000000 – H'BFFFFFF External memory
4 MB
16
CS3
4 H'C000000 – H'CFFFFFF External memory
4 MB
16
CS4
5 H'D000000 – H'DFFFFFF External memory
4 MB
16
CS5
6 H'E000000 – H'EFFFFFF External memory
4 MB
16
CS6
7 H'F000000 – H'FFFFFFF On-chip RAM
1 kB
32
—
Notes: 1. When MD2–MD0 pins are 010
2. When MD2–MD0 pins are 000 or 001
3. For SH7020
4. For SH7021
5. Select with MD0 pin
6. Select with DRAME bit in BCR
7. Divided into 8-bit and 16-bit space according to value of address bit A8 (Long word
accesses are inhibited, however, in on-chip peripheral modules with bus widths of 8
bits. Some on-chip peripheral modules with bus widths of 16 bits also have registers
that are only byte-accessible and registers for which byte access is inhibited. For
details, see the sections on the individual modules.)
8. Divided into 8-bit space and 16-bit space by value of address bit A14
9. Select with IOE bit of BCR
116 HITACHI