HD6437020 Datasheet, PDF (119/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 8.5 Single-Mode DMA Memory Write Cycle States (External Memory Space)
Description
Single-mode DMA Memory Write Cycle States
(External Memory Space)
Bits 15–8:
WAIT Pin Input
DWW7–DWW0 Signal
External Memory
Space
DRAM Space
Multiplexed
I/O
0
Not sampled during Areas 1, 3–5,7: 1 state, Column address 4 states +
single-mode DMA fixed
memory write cycle* _{Areas 0, 2, 6: 1 state +}
long wait state
cycle: 1 state,
fixed (short
pitch)
wait state
from WAIT
1
Sampled during
Areas 1, 3–5, 7: 2 states Column address
single-mode DMA + wait state from WAIT cycle: 2 states +
memory write cycle
(initial value)
Areas 0, 2, 6: 1 state +
long wait state + wait
state from WAIT
wait state from
WAIT (long
pitch)
Note: Sampled in the address/data multiplexed I/O space.
8.2.4 Wait State Control Register 3 (WCR3)
Wait state control register 3 is a 16-bit read/write register that controls WAIT pin pull-up and the
insertion of long wait states. WCR3 is initialized to H'F800 by a power-on reset. It is not
initialized by a manual reset or by the standby mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: WPU A02LW1 A02LW0 A6LW1 A6LW0 —
—
—
Initial value: 1
1
1
1
1
0
0
0
R/W: R/W R/W R/W R/W R/W
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
• Bit 15 (wait pin pull-up control (WPU)): WPU controls whether the WAIT pin is pulled up or
not. When cleared to 0, the pin is not pulled up; when set to 1, it is pulled up.
HITACHI 103