HD6437020 Datasheet, PDF (223/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

9.5 Cautions
1. All registers other than the DMA operations register (DMAOR) and DMA channel control
registers 0–3 (CHCR0–CHCR3) should be accessed in word or long word units.
2. Before rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (when
rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance).
3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the
DMAOR will be set.
4. Interrupt during DMAC Transfer
a. When an NMI interrupt is input, the DMAC stops operation and returns the bus right to the
CPU. The CPU then executes the interrupt processing.
b. When an interrupt other than an NMI occurs.
• When the DMAC is in burst mode.
The DMAC does not return the bus right to the CPU in burst mode. Therefore, even
when an interrupt is requested in DMAC operation, the CPU cannot get the bus right,
causing the interrupt processing not to be executed. When the DMAC completes
transfer and the CPU gets the bus right, the CPU executes the interrupt processing if the
interrupt requested during DMAC transfer is not cleared.*
* Clear conditions for an interrupt request.
 When an interrupt is requested from an on-chip peripheral module, the interrupt factor
flag is cleared.
 When an interrupt is requested by IRQ (edge detection), the CPU begins the IRQ
interrupt processing of the request source.
 When an interrupt is requested by IRQ (level detection), the IRQ interrupt request
signal returned to high level.
• When the DMAC is in cycle-steal mode.
The DMAC returns the bus right to the CPU every when the DMAC completes a
transfer unit in cycle-steal mode. Therefore, the CPU executes the requested interrupt
processing when getting the bus right.
5. The CPU and DMAC leaves the bus right released and the operation of the LSI is stopped
when the following conditions are satisfied.
• The warp bit (WARP) of the bus control register (BCR) of the bus controller (BSC)is set.
• The DMAC is in cycle-steal transfer mode.
• The CPU accesses (reads/writes) the on-chip I/O space.
• Countermeasure
Set the warp bit of BCR to 0 and set it to normal mode.
208 HITACHI