HD6437020 Datasheet, PDF(200/507 Page) Hitachi Semiconductor – SuperH™ RISC engine

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HD6437020 Datasheet, PDF (200/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

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source or destination. When RXI is set as the transfer request, however, the transfer source must

be the SCIâs receive data register (RDR). Likewise, when TXI is set as the transfer request, the

transfer source must be the SCI's transmit data register (TDR).

Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bit

DMA

Transfer

Request DMA Transfer Request

RS3 RS2 RS1 RS0 Source Signal

Desti- Bus Mode

Source nation

0 1 0 0 SCI0

RXI0 (SCI0 receive data full RDR0 Any* Cycle steal

receiver interrupt transfer request)

0 1 0 1 SCI0

TXI0 (SCI0 transmit data

trans- empty interrupt transfer

mitter request)

Any

TDR0 Cycle steal

0 1 1 0 SCI1

RXI1 (SCI1 receive data full RDR1 Any* Cycle steal

receiver interrupt transfer request)

0 1 1 1 SCI1

TXI1 (SCI1 transmit data

trans- empty interrupt transfer

mitter request)

Any* TDR1 Cycle steal

1 0 0 0 ITU0

IMIA0 (ITU0 input capture A/ Any*

compare-match A)

Any* Burst/Cycle

steal

1 0 0 1 ITU1

IMIA1 (ITU1 input capture A/ Any*

compare-match A)

Any* Burst/Cycle

steal

1 0 1 0 ITU2

IMIA2 (ITU2 input capture A/ Any*

compare-match A)

Any* Burst/Cycle

steal

1 0 1 1 ITU3

IMIA3 (ITU3 input capture A/ Any*

compare-match A)

Any* Burst/Cycle

steal

SCI0, SCI1: Serial communications interface channels 0 and 1

ITU0âITU3: Channels 0â3 of the 16-bit integrated-timer pulse unit.

RDR0, RDR1: Receive data registers 0, 1 of SCI

TDR0, TDR1: Transmit data registers 0, 1 of SCI

Note: External memory, memory-mapped external device, on-chip memory, on-chip peripheral

module (excluding DMAC)

When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt

enable bits must be set to output the interrupt signals. Note that transfer request signals from on-

chip peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU

as well. When an on-chip peripheral module is specified as the transfer request source, set the

priority level values in the interrupt priority level registers (IPRCâIPRE) of the interrupt controller

(INTC) at or below the levels set in the I3âI0 bits of the CPUâs status register (SR) so that the

CPU does not acknowledge the interrupt request signal.

HITACHI 185

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