HD6437020 Datasheet, PDF (372/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Table 13.4 Bit Rates and BRR Settings in Clocked Synchronous Mode
φ (MHz)
Bit Rate
2
(bits/s) n N
4
nN
8
nN
10
nN
16
nN
110
3 70
——
——
——
——
250
2 124 2 249 3 124 — — 3 249
500
1 249 2 124 2 249 — — 3 124
1k
1 124 1 249 2 124 — — 2 249
2.5k
0 199 1 99 1 199 1 249 2 99
5k
0 99 0 199 1 99 1 124 1 199
10k
0 49 0 99 0 199 0 249 1 99
25k
0 19 0 39 0 79 0 99 0 159
50k
09
0 19 0 39 0 49 0 79
100k
04
09
0 19 0 24 0 39
250k
01
03
07
09
0 15
500k
0 0√
01
03
04
07
1M
0 0*
01
—— 0 3
2.5M
— — 0 0* — —
5M
——
Note Settings with an error of 1% or less are recommended.
Blank: No setting available
—: Setting possible, but error occurs
√ : Continuous transmit/receive not possible
The BRR setting is calculated as follows:
Asynchronous mode
N = [φ/(64 × 2^{2n – 1} × B)] × 10⁶ – 1
Clocked synchronous mode
N = [φ/(8 × 2^{2n – 1} × B)] × 10⁶ – 1
B: bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: φ frequency (MHz)
n: baud rate generator clock source (n = 0, 1, 2, 3)
For the clock sources and values of n, see table 13.5.
20
nN
——
——
——
——
2 124
1 249
1 124
0 199
0 99
0 49
0 19
09
04
01
0 0*
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