HD6437020 Datasheet, PDF (162/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

CK
A21–AD0
RAS
CAS
WR
Read
AD15–AD0
WR
Write
AD15–AD0
T_p
T_r
T_c1
T_c2
T_c1
T_c2
Column address 1 Column address 2
Row address 1
Data 1
Data 2
Data 1
Data 2
Figure 8.26 Long Pitch High-Speed Page Mode (Read/Write Cycle)
RAS Down Mode and RAS Up Mode: Sometimes access to another area can occur between
accesses to the DRAM even though burst operation has been selected. Keeping the RAS signal at
low while this other access is occurring allows burst operation to continue the next time the same
row of the DRAM is accessed. The RASD bit in the DCR selects the RAS down mode when set to
1 and the RAS up mode when cleared to 0. In both RAS down mode and RAS up mode, burst
operation is continued while the same row address continues to be accessed, even if the bus master
is changed.
• RAS Down Mode: When the RASD bit of DCR is set to 1, the DRAM access pauses and the
RAS signal is held low throughout the access of the other space while waiting for the next
access to the DRAM area. When the row address for the next DRAM access is the same as the
previous DRAM access, burst operation continues. Figure 8.27 shows the timing of the RAS
down mode when external memory space is accessed during burst operation.
The RAS signal can be held down in the DRAM for a limited time; the RAS signal must be
returned to high within the specified limits even when the RAS down mode is selected since
the critical low level period is set. In this LSI, even when the RAS down mode is selected, the
RAS signal automatically reverts to high when the DRAM is refreshed, so the BSC’s refresh
control function can be employed to set a CAS-before-RAS refresh that will keep operation
within specifications. See section 8.5.6, Refresh Control, for details.
146 HITACHI