HD6437020 Datasheet, PDF (297/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

CK
TCNT
Overflow
signal
OVF
H' FFFF
H' 0000
OVI
Figure 10.56 Timing of Setting OVF
10.5.2 Clear Timing of Status Flags
The status flags are cleared by a write cycle in which 1 is read on the CPU and then 0 is written to
it. This timing is shown in figure 10.57.
TSR write cycle
T1
T2
T3
CK
Address
IMF, OVF
TSR address
Figure 10.57 Timing of Status Flag Clearing
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