HD6437020 Datasheet, PDF (126/507 Pages) Hitachi Semiconductor – SuperH™ RISC engine

Bit 5: CKS2
0
1
Bit 4: CKS1
0
1
0
1
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
Clock input disabled (initial value)
φ/2
φ/8
φ/32
φ/128
φ/512
φ/2048
φ/4096
• Bits 2–0 (reserved): These bits always read as 0. The write value should always be 0.
8.2.8 Refresh Timer Counter (RTCNT)
The refresh timer counter (RTCNT) is a 16-bit read/write register that is used as an 8-bit upcounter
that generates the refresh or interrupt request. When the input clock is selected by clock select bits
2–0 (CKS2–CKS0) in RTCSR, that clock makes the RTCNT start incrementing. When the values
of RTCNT and the refresh time constant register (RTCOR) match, RTCNT is cleared to H'0000
and the CMF flag of the RTCSR is set to 1. When the RFSHE bit of the RCR is also set to 1, a
CAS-before-RAS refresh is performed. When the CMIE bit of the RTCSR is also set to 1, a
compare match interrupt (CMI) is generated.
Bits 15–8 are reserved bits and do not count. These bits always read as 0.
RTCNT is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by
the standby mode.
To prevent RTCSR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'69 is written in the top byte and the
actual data is written in the lower byte. For details, see section 8.2.11, Register Access.
110 HITACHI